Showing results: 481 - 495 of 1086 items found.
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Euresys Inc.
S2I’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. This minimizes development time and allows for top-notch performance at a small footprint, while leaving enough flexibility to customize the design. Sensor to Image cores are compact and leave enough space in the FPGA for your application.
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FMC424 -
Sundance Multiprocessor Technology Ltd.
The FMC424 is a dual QSFP+ FPGA Mezzanine Card. Electrically compliant with the VITA 57.1 standard the FMC424 is compatible with 4DSP FPGA carrier cards offering High Pin Count connectors. It also allows for the option to stack an additional FMC over it. Any of the 4DSP FMC that use LVDS and single ended signaling only can be mounted over the FMC424, thus offering users with the ability to build a complete high speed data acquisition, waveform generation and optical communication solution while using a single FMC site on an FPGA carrier card.
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DapTechnology B.V.
Synthesizable 1394 and AS5643 IP Core solutions PHY, LLLC, PHY & LLC for multiple FPGA families.
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GX3788 -
Marvin Test Solutions, Inc.
The GX3788 is a user configurable, FPGA-based, 3U PXI multi-function card which supports digital and analog test capabilities. The card employs the Altera Stratix III FPGA which features over 45,000 logic elements and 1.836 Kb of memory. The GX3788 is based on the GX3700 FPGA card and includes an integral daughter board which provides (8) differential input, 16-bit, 250 MS/s A to D converters and (8), 16-bit, 1 MS/s, D to A converters. The module's FPGA is pre-programmed, providing access to all digital and analog functions. Alternatively, users can program or modify the FPGA , allowing user to adapt the module to their own specific test needs. The design of the FPGA is done by using Altera's free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded into the FPGA directly or via an on-board EEPROM.
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5560 Family -
CAEN S.p.A.
CAEN recently opened the doors of its R&D to the open FPGA technology, which is becoming more and more widely used and required. In addition, we decided to invest many resources in order to make this technology accessible to everyone. These efforts result in the brand new x5560 Programmable Digitzer family and the SCI-Compiler software for easy-programming of the open FPGA.
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Aldec, Inc.
Aldec and Microchip have joined together, offering a new, innovative, reprogrammable prototyping solution for Microchip RTAX-S/S and RTSX-SU space-flight system designs. Unlike the traditional OTP (One Time Programmable) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microchip ProASIC®3E FPGA technology, for design prototype re-programmability.
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GaGe
Digital signal processing routines can be conducted on raw signal data acquired by GaGe high-speed digitizers either directly on the onboard FPGA of the digitizer card via our eXpert FPGA firmware features or can be optionally conducted on GPU cards receiving real-time streaming of raw signal data acquired by GaGe high-speed digitizers via the PCIe interface.
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Model 7070-317 -
Pentek, Inc.
- Supports Xilinx Virtex-7 VXT FPGA- GateXpress supports dynamic FPGA reconfiguration across PCIe- Eight 250 MHz 16-bit A/Ds- Eight multiband DDCs- 4 GB of DDR3 SDRAM- Sample clock synchronization to an external system reference- PCI Express (Gen. 1, 2 and 3) interface up to x8- Optional optical Interface for backplane gigabit serial interboard communication- Optional LVDS connections to the Virtex-7 FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 AND VITA-66.4 and VITA-65 (OpenVPX™ System Specification)- Also available as Model 5973-317
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Model 7070-316 -
Pentek, Inc.
- Supports Xilinx Virtex-7 VXT FPGA- GateXpress supports dynamic FPGA reconfiguration across PCIe- Eight 250 MHz 16-bit A/Ds- 4 GB of DDR3 SDRAM- Sample clock synchronization to an external system reference- PCI Express (Gen. 1, 2 and 3) interface up to x8- Optional optical Interface for backplane gigabit serial interboard communication- Optional LVDS connections to the Virtex-7 FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 AND VITA-66.4 and VITA-65 (OpenVPX™ System Specification)- Also available as Model 5973-316
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Model 5973-316 -
Pentek, Inc.
- Supports Xilinx Virtex-7 VXT FPGA- GateXpress supports dynamic FPGA reconfiguration across PCIeEight 250 MHz 16-bit A/Ds- 4 GB of DDR3 SDRAM- Sample clock synchronization to an external system reference- PCI Express (Gen. 1, 2 and 3) interface up to x8- User-configurable gigabit serial interface- Optional optical Interface for backplane gigabit serial interboard communication- Optional LVDS connections to the Virtex-7 FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 AND VITA-66.4 and VITA-65 (OpenVPX™ System Specification)Ruggedized and conduction-cooled versions available
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Model 5973 -
Pentek, Inc.
- VITA-57.1 FMC site offers access to a wide range of possible I/O- Supports Xilinx Virtex-7 VXT FPGAs- GateXpress supports dynamic FPGA reconfiguration across PCIe4 GB of DDR3 SDRAM- PCI Express (Gen. 1, 2 and 3) interface up to x8- User-configurable gigabit serial interface- LVDS connections to the Virtex-7 FPGA for custom I/O- Optional optical interface for backplane gigabit serial interboard communication- Compatible with several VITA standards including: VITA-46, VITA-48 AND VITA-66.4 and VITA-65 (OpenVPX™ System Specification)- Ruggedized and conduction-cooled versions available
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Curtiss-Wright Defense Solutions
Digital Down Conversion (DDC) FPGA IP cores are available supporting Xilinx Virtex-5, Virtex-6 and Virtex/Kintex-7 FPGAs. The DDC family of IP cores support decimation from 2 to 64 in complex mode and from 2 to 32 in real mode. The DDC is available as embedded IP within a number of Curtiss-Wright ADC products or in a source format.
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Model 5973-317 -
Pentek, Inc.
- Supports Xilinx Virtex-7 VXT FPGA- GateXpress supports dynamic FPGA reconfiguration across PCIe- Eight 250 MHz 16-bit A/Ds- Eight multiband DDCs- 4 GB of DDR3 SDRAM- Sample clock synchronization to an external system reference- PCI Express (Gen. 1, 2 and 3) interface up to x8- User-configurable gigabit serial interface- Optional optical Interface for backplane gigabit serial interboard communication- Optional LVDS connections to the Virtex-7 FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 AND VITA-66.4 and VITA-65 (OpenVPX™ System Specification)Ruggedized and conduction-cooled versions available
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Data Patterns Pvt. Ltd.
The FPGA Mezzanine Card is used by Data Patterns to implement signal interface with external world compatible FPGAs mounted on the FMC carrier there are primarily used for high speed analog interface for digitization (ADCs) and waveform generation (DACs). This form factor is also utilized for special I/O Interfaces such as various avionic protocols and buses. FMC I/O signals may be routed via front panel connectors or through Mezzanine connectors that route the signal back to the carrier board for routing through rear I/O of the Chassis. The system interface is designed for routing to FPGAs using a VITA 57 0.05 Pitch Terminal Array Assembly.