Company: Cadence Design Systems
Concerned about your test costs? Reduce your SoC test time by up to 3X with the Cadence® Modus™ Test Solution. Introducing a new patent-pending 2D Elastic Compression architecture, this next-generation tool enables compression ratios beyond 400X without impacting design size or routing. With a complete suite of industry-standard capabilities for memory BIST, logic BIST, testpoint insertion, and diagnostics, the solution can help you reduce your production test costs and increase silicon profit margins.