TestKompress® is an automatic test pattern generation (ATPG) tool that provides the highest quality scan test with the absolute lowest test cost. TestKompress has an industry-proven ATPG engine that applies effective fault models to your entire logic design. Manufacturing test costs are held in check by an award-winning test pattern compression technique called Embedded Deterministic Test (EDT™).
LogicVision's ETCompression is a deterministic test compression solution that builds upon the LogicVision's embedded logic test capabilities. ETCompression provides test time and test volume compression values equal to other 3rd party compression solutions, but also offers true at-speed launch-on-shift test application using LogicVision's patented Burst-Mode test timing architecture.
Automatic Test Pattern Generation Tools (known as VICTORY) are comprehensive set of software tools that are used to generate test-patterns and obtain diagnostic information for electronic assemblies containing boundary scan devices. The toolset also includes testability analysis tools for designing boards with boundary scan devices. VICTORY was introduced in 1991, one year after IEEE adopted the 1149.1 boundary scan standard.
VirtualScan is SynTest's solution to combat increase in test data volume and test cycle volume. With VirtualScan (VS) an extremely large number of short scan chains within the SOC can be virtually accessed from outside the chip with a limited number of pins assigned as scan pins.
TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It's the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys' patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compact tests for even the most complex designs.
TurboScan is an advanced full-scan and partial-scan test suite. It includes a Scan Synthesizer and an Automatic Test Pattern Generator (ATPG). TurboScan automatically repairs testability violations to make your design highly testable.
NEBULA provides advanced features for performing early validation of DFT infrastructure and ATPG patterns in first silicon. The NEBULA solution directly imports test pattern formats and DFT information from leading EDA vendor tools, such as Synopsys' TetraMAX and Cadence's Encounter Test.
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow
The SpyGlass®-DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass-DFT solution not only detects testability issues--it can also automatically correct them.
Since 1979, TDS has been used by generations of test engineers. TDS established many standard formats and methodoglies. WGL was TDS's contribution to the industry, and has been used as the primary standard test interface language by ATPG tools before STIL. Flow-based conversion methodology has been standardized in many top electronics firms. Supported EDA Formats: Scan Patterns: STIL, WGL Functional Patterns: VCD, EVCD. 30+ legacy formats: standard SCII, TITDL, and more.
Solstice helps design and test teams to work in the same environment, using waveforms as the universal communication language. Scan and functional patterns (ATPG, BIST, STIL, WGL, various ATE formats), including those from IP-core vendors, can be validated with the designer's DUT model for advanced preparation of test patterns, and more importantly, to perform early detection of problems that would cost millions of dollars if they slipped through tape-out into mask and silicon manufacturing proc...
Direct conversion from cycle driven simulation data (ATPG scan patterns) (WGL/TDL/STIL) to tester. TDL/WGL/STIL to tester conversion Supports STIL ext 0,1,2 constructs Easy to use and cost effective conversion solution Optimize tester resources usage Supports advanced tester features (Such as Xmode, Multi-port etc’) Compress and minimize vectors count Allow direct tester binary patterns creation
onTAP provides comprehensive boundary-scan test development tools with powerful run time software including pin-level diagnostics. onTAP provides everything required for robust JTAG test solutions. Robust ATPG for high fault coverage and precise pin-level diagnostics. Interconnect, Bus Wire, Pull-up/Pull-down, TAP Infrastructure tests, Shorts and Opens. Memory/Cluster tests employ Virtual Pins to test non-JTAG memory and FLASH devices.