Showing results: 16 - 29 of 29 items found.
-
ONYX Apps
LatencyMeter measures the real-world Round Trip Latency (RTL) of a given iOS audio system. It functions by playing short test tones while simultaneously recording (listening for) the tones to return back to the input.
-
360 EC-RTL -
OneSpin Solutions GmbH
During a typical development process, there are many occasions where a change needs to be made to a block, which must then be retested to ensure functional equivalence. For example, once a block has been proven to operate correctly, a designer may wish to optimize some section, maybe to improve the coding style, reduce the gate count or streamline operation. Today, an engineer must execute an entire simulation regression run to verify each change. This often requires a lot of time and may also need additional stimulus, with no guarantee that an exhaustive functional check will be performed.
-
Ascent XV -
Real Intent, Inc.
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
-
OneSpin Solutions GmbH
ASIC synthesis verification from RTL code to final netlist.Systematic design errors, introduced by automated design refinement tools, such as ASIC synthesis, can be hard to detect, and damaging if they make it into the final device. Formal Equivalency Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized code.
-
TySOM -
Aldec, Inc.
The TySOM Embedded Development Kit is for the embedded designer who needs a high-performance RTL simulator/debugger for their embedded applications such as IoT, Factory Automation, UAV and Automotive. The kit includes Riviera-PRO Advanced Verification Platform and a Xilinx Zynq development board that contains single Zynq chip (FPGA + Dual ARM Cortex-A9), memories (DDR3, uSD), communication interfaces (miniPCIe, Ethernet, USB, Pmod, JTAG) and multimedia interfaces (HDMI, audio, CMOS camera).
-
HES-DVM -
Aldec, Inc.
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
-
SpecInsight -
CM Engineering Co., Ltd.
The keys to functional verification are “verification strategy” and “highly complete verification item extraction.” Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.
-
Rhein Tech Laboratories, Inc.
Rhein Tech Laboratories, Inc. (RTL) is a full-service design and compliance engineering test laboratory. We have grown with the industry from general purpose EMC testing into other areas of testing such as Radio (RF testing), Military and Aviation, Industrial, Scientific and Medical, Automotive, Electrical Safety, Shielding Effectiveness, Site Surveys and Radar Cross Section & High Range Resolution measurements.
-
Soundwire -
Arasan Chip Systems, Inc.
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
-
Nlview -
Concept Engineering GmbH
Concept Engineering's Nlview engine provides automatic generation of schematic diagrams for different levels of electronic circuits, including gate-level, RTL and block-level. Optional engines are available for the system-level (S-engine) and for the transistor-level (T-engine). The schematic layout can be modified and controlled by human intervention and always optimized by algorithms. A fine granularity of user preferences can be mixed with machine computed "beauty" to get the best human readable diagrams. Interactive circuit exploration is supported by incremental schematic generation technology. Nlview provides a set of APIs and interfaces with a certain GUI environment. Please see also the Nlview Widgets datasheet (PDF file).
-
12C/ 12S/ SPI/ UART -
Arasan Chip Systems, Inc.
Arasan has a diverse portfolio of connectivity IP products including SPI, I2C, I2S and UART. These protocols are vital for the integration of SoCs with peripheral chipsets in order to form a complete hardware platform. They are frequently used by the SoC to configure, control and gather diagnostic information at the platform level to ensure correct operation of the hardware.Arasan's proven Connectivity IP Solutions provides a risk free path to integrating these interfaces in SoC designs:High quality IP cores ensure inter-operability between SoCs and peripheralsIn-house domain expertise ensures a high quality support throughout the SoC development cycleTotal IP solution includes RTL source code, synthesis scripts, test environment and documentation
-
TySOM EDK -
Aldec, Inc.
The TySOM™ Embedded Development Kit is for the embedded designers who need a high-performance RTL simulator/debugger for their embedded applications such as IoT, Automotive, Factory automation, UAV and Robotics. The kit includes Riviera-PRO™ Advanced Verification Platform and a TySOM development/prototyping board. TySOM boards come with either a Zynq 7000 chip (FPGA + Dual ARM® Cortex™-A9) or with a Zynq® UltraScale+™ MPSoC device. These boards include memories, and various communication and multimedia interfaces in addition to FMC connectors for peripheral expansion. Reference designs for application such as IoT, ADAS, 4K UltraHD imaging and Robotics and a complete reference design, which contains the SW (Linux) and all the hardware blocks required to support the peripherals on the board, are provided.
-
RocketSim -
Cadence Design Systems
Complementing compiled-code simulators, Cadence® RocketSim™ parallel simulation engine eliminates functional verification bottlenecks by speeding up simulation using commonly available multi-core servers. The engine is proven for register-transfer level (RTL) system on chip (SoC), gate-level functional simulation, and gate-level design for test (DFT) simulation in numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains. Ever-growing chip density and complexity slow down simulation, making functional verification a severe bottleneck. As a result, chip design projects miss their time-to-market targets, or designers end up taping out early with less confidence. RocketSim parallel simulation engine solves the bottleneck common in existing compiled-code simulators by offloading the time-consuming calculations to an ultrafast multi-core engine.
-
Avery Design Systems
Level up and perform full System HW-SW verification at pre-silicon levelIterate HW and SW changes 10X faster at RTL compared to FPGA or system prototypesBegin HW-SW integration much sooner in development processVirtual machine to VIP co-sim/co-emulate environment extends existing SV/UVM testbench + VIPsX86 HostSupports PCIe/CXL root complex VIPRun Linux kernel drivers, compliance and benchmarking programs, and application softwareArm, RISC-V embedded systemsSupports AMBA (AXI/AHB/APB) VIPRun bare metal code or RTOS embedded systemsRun OS and SW unmodified from actual system configurationDebug trace shows QEMU to remote PCIe/CXL/AXI ports transactionsAvery's implementation of QEMU co-simulation is optimized for fastest performance including KVM mode and iWARP technologySimulations are scalable to 10s to 100s of instances for regression over OS versions and HW configurations
