Showing results: 1 - 15 of 29 items found.
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Blue Pearl Software Inc
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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LogicVision, Inc.
The PowerPro RTL Low-Power Platform provides a complete solution to accurately measure, interactively explore and thoroughly optimize power during the RTL development cycle.
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DeFacTo Technologies
Before logic synthesis, STAR enables full implementation capabilities towards IP and connectivity insertion with a real-time monitoring of the integration progress. This enables SoC creation in minutes and maximize design reuse from existing projects.
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ConStruct -
Excellicon Inc.
ConStruct is an early RTL Floorplanner, partition explorer, and floorplan verification tool. It can further be used to generate the partitioned RTL based on specified criteria.
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DeFacTo Technologies
Defacto’s STAR is also an application development environment for CAD Teams to develop in-house and custom RTL applications. It allows multi-APIs access to “RTL Build & Signoff” capabilities with higher flexibility beyond Tcl.
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RTLvision -
Concept Engineering GmbH
RTLvision PRO provides easy RTL debugging and fast visualization of RTL code, so that engineers can easily understand, implement and optimize VHDL, Verilog or SystemVerilog code. Please check out the Demo Videos: Basic Features and Clock Tree Analyzer.
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Ascent Lint -
Real Intent, Inc.
Ascent Lint is a state-of-the-art RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.
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Allegro DVT
Hardware (RTL) video encoding, decoding and codec IP cores
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ALINT-PRO -
Aldec, Inc.
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
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SD 3.0 / eMMC 4.51 IP Family -
Arasan Chip Systems, Inc.
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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EL & Associates, Inc.
EL & Associates, Inc. specializes in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. We engage with customers from RTL phase to silicon prototype. The ELA methodology is optimized to manage risk in design, manufacture and product deployment. ELA has successfully completed over 750 designs to date.
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DeFacTo Technologies
Defacto’s STAR augments existing RTL verification flows by providing fully automated structural checks. Users can also define and build their custom checks.
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OneSpin Solutions GmbH
Functional correctness of FPGA synthesis from RTL code to final netlist. Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.
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Verix PhyCDC -
Real Intent, Inc.
Verix PhyCDC is the only solution that delivers precise netlist CDC sign-off including glitch checking. RTL CDC sign-off assumptions may become invalid because of logic synthesis and power optimizations. Verix PhyCDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains are CDC-safe at the gate level. Complementing Real Intent’s Verix CDC solution that provides comprehensive analysis for RTL sign-off, Verix PhyCDC delivers the most advanced netlist sign-off for giga-gate designs.
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DFT- PRO Plus -
Syntest Technologies
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow