Showing results: 31 - 45 of 45 items found.
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IPC/JEDEC J-STD-020D.1 -
National Technical Systems
The advent of surface mount devices (SMDs) introduced a new class of quality and reliability concerns regarding package damage ”cracks and delamination” from the solder reflow process. This document describes the standardized Moisture Sensitivity Levels (MSL) of floor life exposure for moisture/reflow-sensitive SMD packages along with the handling, packing and shipping requirements necessary to avoid moisture/reflow-related failures. Companion documents J-STD-020D.1 and JEP113 define the classification procedure and the labeling requirements, respectively.
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Thermo Fisher Scientific Inc.
Identify and help correct ESD and latch-up susceptibility issues on sensitive integrated circuit components prior to full-scale production with the Thermo Scientific™ MK.2-SE ESD and Latch-Up Test System. The MK.2-SE test system provides advanced capabilities to test high pin count IC devices to Human Body Model (HBM) and Machine Model (MM) ESD standards. The system’s pulse delivery design addresses wave form hazards such as trailing pulse and pre-discharge voltage rise, and performs Latch-Up testing per the JEDEC EIA/JESD 78 Method.
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Thermal Engineering Associates, Inc.
TEA offers a series of thermal test boards for package characterization and design comparison that conform to to the JEDEC JESD51 standards. The board family, referred to as the TTB-1000 series, consists of two different standard sizes designed to cover a wide range of package sizes. These boards, also referred to as test coupons, provide a well defined mounting environment, will withstand temperatures to 125 oC, and have lead lands terminated in eyelets to allow for hand-wired connection to the board edge contacts. The board mates with a dual 18-pin, 3.962 mm (0.156") pitch edge-card connector.
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WT-100 -
Thermal Engineering Associates, Inc.
The WT-100 Forced Convection (Moving Air) Wind Tunnel is designed in accordance with the EIA/JEDEC JESD51-6 standard for thermal characterization of semiconductor packages and devices. The vertical design minimizes laboratory floor space requiements. Air is drawn in at the bottom and exhausts at the top. The test section is large enough to accommodate the largest JEDEC and SEMI thermal test boards. Air velocity can be adjusted over the range of 0.5 to 5 m/s; air velocity is monitored with an included hot-wire anemometer connected to a digital display. A Type-T thermocouple is mounted in the test section for monitoring the moving air temperature.
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SD Card v.3.0 / eMMC v.4.51 IP Family -
Arasan Chip Systems, Inc.
Designed for embedded applications that require high performance, small form factor, and high storage capacity, eMMC provides the support for embedded mass storage memory on embedded host systems. The eMMC protocol simplifies the access to NAND flash memories (such as MLC) to the host by hiding the functional differences among suppliers. Compliant to the latest JEDEC eMMC specifications, Arasan’s eMMC IP supports power-on-booting without the upper level software driver. The explicit sleep mode allows the host to instruct the controller to directly enter the sleep mode. The interface supports interface voltage of either 1.8V or 3.3V.
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ACMAS Technologies Pvt. Ltd.
WEIBER climatic test chamber is ideally suited for specimen test requiring quick changes of temperature. It covers various applications from JEDEC and IEC test standards. The climatic chamber is equipped with advanced technology such as specimen temperature control which allows linear specimen temperature rates of change during rapid thermal cycling or accurate temperaThe walk in option provides facility to test large sized, heavy weight specimen as well as the facility to test the specimen in bulk. Capacities ranging from 2000 to 10,000 Lt are available. Standard as well as customizable sizes and facilities are provided.
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HBM-VT -
High Power Pulse Instruments GmbH
- HBM pulse generator verification tester according ANSI/ESDA/JEDEC JS-001 up to ±10kV- To be used in HBM test and qualification labs for regular pulse generator specification compliance test in order to fulfill lab audit and certification requirements- Fully automatic compliance test and verification of HBM pulse generators regarding ANSI/ESDA/JEDEC JS-001 normative standard at 3 different load conditions: Short Circuit, 500 Ω, and a reference diode at VBR=15 V reverse breakdown voltage, including DC test- Parameter evaluation and verification of the transient HBM current waveforms: Peak Current, Rise Time, Decay Time, Maximum Ringing Current- Optionally available upgrade for all HPPI TLP-3010C, 4010C, 8010A, 8010C, HBM-TS10-A hardware systems in combination with HBM-S1-B (6kV) pulse generators (upgrade on request)- Fully automatic test report generation (PDF)- Electrically floating (no fixed system ground): The HBM loads, current sensor output, USB control interface and the enclosure are electrically floating. There is no limiting system ground which may introduce common-mode interference induced HBM current measurement errors.- Isolated industrial full-speed USB control interface- Isolated power supply derived from USB port- Compact size 126mm x 82.5mm x 44.5mm
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LPDDR3 -
FuturePlus Systems
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured States at 1600MT/sContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsMode Register Listing providedSupports Auto-Clock rate detect and clock stoppageConnects to the target under test with Flying Lead, BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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Advantech Co. Ltd.
Advantech Memory module and DRAM modules offer an extensive portfolio of industrial grade memory, like un-buffered DIMMs, LONG-DIMM and SO-DIMM which are designed according to the latest JEDEC standards and cover all technologies from DDR to DDR3 memory in wide temp ranges (-40 to 85C). Advantech Memory module and DRAM modules'' synchronous design allows precise cycle control with the use of system clock. I/O data transactions are possible on both edges of DQS. Range of operation frequencies, and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
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SC -
Ardent Concepts, Inc.
Ardent Concepts Test Sockets for ATE test deploy patented SC Contact Sets. This technology is capable of over 2 Million mechanical insertions in production environments and uses easy to replace pins with no complicated assembly procedure. It is designed to be drop-in compatible with 1mm offset and straight through footprints to ease implementation, and RC SC’s simple and robust design is extremely cost effective when compared with existing “roll” type test contactors and sockets. Designed specifically for JEDEC QFN and MLF applications, SC High Performance Test Sockets are available for most handler set-ups and offer exceptional AC performance.
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Hanwa Electronic Ind. Co.,Ltd.
◆Correspond to 300mm Wafer. This tester can measure LED or the large sizes Wafer, such as a system LSI. And Zap of HBM/MM can be performed. The Automatic destructive judging by V/I measurement can also be performed after Zap.◆Waveform guarantee in Zap needles. HED-W5100D carries out the calibration before shipment in the place of Zap needles. Therefore, Correlation of the Result of a Package Device becomes clear easily.◆Correspondence to Standards This Tester corresponds to the Standard of JEITA, ESDA, and JEDEC. A Zap unit adopts the plug-in system and also has the waveform of Customer's requests.◆Connection with TLP This Tester is the best for TLP Testing with deep relation of ESD. The protection circuit of a device with an ESD problem is investigated.
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DDR3 -
FuturePlus Systems
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured StatesContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsRow Hammer Analysis for potential data corruptionInteractions among up to 8 ranks, over two slots are analyzed.Mode Register Listing providedSupports Auto-Clock rate detect and clock stoppage Connects to the target under test with DIMM, SO-DIMM, and BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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UFS -
Arasan Chip Systems, Inc.
Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. The UFS is also adopted by MIPI as a data transfer standard designed for mobile systems. Most UFS applications require large storage capacity for data and boot code. Applications include mobile phones, tablets, DSC, PMP, MP3, and other applications requiring mass storage, boot storage, XiP or external cards. The UFS standard is a simple, but high-performance, serial interface that efficiently moves data between a host processor and mass storage devices. USF transfers follow the SCSI model, but with a subset of SCSI commands.The Arasan UFS IP family consists of Host controller IP, Device controller IP, and MPHY.
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DDR4 -
FuturePlus Systems
Provides logic analyzer like deep transaction Listing and Waveform captureCan store up to 1G of captured StatesContinuous, real time analysis, not post-processingEye Detector guarantees valid data acquisitionExtensive Triggering and Storage Qualification allows precise insightProtocol Violation Detector provides hundreds of simultaneous, real time tests to JEDEC specificationsMargin analysis shows where command timing fails and where it can be improvedThousands of counters for DDR4 analyze performance metrics real time, all the time, for all commands, total Clocks, by Rank also power management informationInteractions among up to 8 ranks, over two slots are analyzed.Mode register and SPD capture are providedSupports Auto-Clock rate detect and clock stoppageConnects to the target under test with DIMM, SO-DIMM, and BGA interposers or a midbus probeIntegrated Microsoft Charts gives quick insight into large trace capturesTrigger In & Out allows the Detective to integrate with other test tools
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ATSS Series -
Thermotron Industries
Thermotron's Automated Thermal Stress Systems (ATSS) facilitate extremely rapid product temperature change rates in a space-saving, self-contained design that accelerate a Thermal Stress test. Thermotron's ATSS chambers meet the latest MIL-STD 883E and MIL-STD 202F thermal shock specifications as well as JEDEC and IPC test methods. ATSS chambers are capable of the following: Rapid thermal shocking, Accelerated product stressing, Controlled thermal cycling in a self-contained, compact design. With separate hot and cold zones, the Automated Thermal Stress System was designed with a patented retractable product transfer carrier that makes full use of the available working volume in both temperature zones for increased product loading and throughput. The product transfer carrier reduces the overall height requirements of the chamber and is made as light as possible to minimize thermal loading restraints. Thermotron ATSS chambers can be used as part of most commercial reliability and quality control programs, helping to determine:
