Verilog
-
product
Graphical Debugging for Verilog, VHDL, and C++ Simulators
BugHunter Pro
BugHunter uses the SynaptiCAD graphical environment and supports all major HDL simulators. It has the ability to launch the simulator, provide single step debugging, unit-level test bench generation, streaming of waveform data, project management, and a hierarchy tree. The unit-level test bench generation is unique in that it lets the user draw stimulus waveforms and then generates the stimulus model and wrapper code and launches the code. It is one of the fastest ways to test a model and make sure that everything is working correctly. The debugger also has exceptional support for VCD waveform files.
-
product
EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
-
product
Verification IP's
SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
-
product
MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
-
product
Design Verification Editor Checker for SV/UVM
DVinsight
DVinsight-Pro is a Integrated Development Environment (IDE) for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code. Design & Verification Engineers can create correct by construction DV code because DVinsight-Pro is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards.
-
product
RTL debugger and viewer for Verilog and VHDL
RTLvision
RTLvision PRO provides easy RTL debugging and fast visualization of RTL code, so that engineers can easily understand, implement and optimize VHDL, Verilog or SystemVerilog code. Please check out the Demo Videos: Basic Features and Clock Tree Analyzer.
-
product
SystemVerilog, VHDL & Unified Power Format (UPF) Parser Platforms
Verific Design Automation, Inc.
SystemVerilog (which includes Verilog 2001) and VHDL are parsed and processed in two steps, analysis and elaboration. Mixed VHDL and SystemVerilog compilation is fully supported. UPF is processed in a single step, analysis.
-
product
Emulate Test in simulation
STIL-VT
Emulate test patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test patterns. Reads the intermediate STIL format of tester patterns and creates a Verilog /VHDL simulation test bench. (A sub-set of Virtual tester solution)
-
product
Static Design Verification
ALINT-PRO
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
-
product
Virtual tester
Emulate tester patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test programs. Reads the actual ATE program and creates a Verilog /VHDL simulation test bench.
-
product
BSDL models for Verilog, LASAR, HILO
MODBSDL
MODBSDL Software reads a BSDL file and writes an ACUGEN-format simulation model. This model can then be simulated and fault graded using ACUGEN's ATGEN product, or converted to another simulation format.
