DFT Consulting SiliconAid Solutions provides expert consulting services for all aspects of semiconductor Design-for-Test (DFT) development and implementation.

V520 - DFT-Optimized Engineering Test Platform The Teseda V520 is the first engineering test platform designed specifically for scan validation, silicon debug and failure analysis, not just as a general-purpose tester adapted for scan test. The Teseda V520 works with the Teseda WorkBench™ DFT-Intelligent™ software and your Design-for-Test (DFT) tools for effortless integration with the chip design environment.

DFT Services Test Coach has published "Design for Test" (DFT) notes to help ensure a bed-of-nails test fixture can be fabricated to test a PCB without sacrificing test coverage. This covers test point size and spacing as well as many other considerations. In some cases not all requirements can be met.

Polyphase DFT ( Ventrix Range ) The Polyphase DFT, sometimes referred to as the WOLA (Weighted OverLap and Add) is an efficient method used to implement a uniformly distributed multi-channel filter bank. The architecture consists of a polyphase front-end that performs the weighting, overlapping and addition followed by a DFT that is usually implemented using an FFT. The Polyphase DFT is generally used in applications that demand high quality filters in terms of stop band rejection and filter shape.

DFT Analysis Services Involve ECT as early as possible in your design cycle to # Reduce cost # Improve product Quality # Impact total cost of ownership Design for Test services include: # CAD, Schematic and BOM review # Strategy recommendations # Access analysis and test point reduction # Testability analysis # Test point size, spacing and proximity analysis # ECT exclusive front-end tool

DFT and BIST Course Course teaches: all aspects of Design for Testability, what built-in [self] test (BIST) is and how it can be specified. You will learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators.

TestWay - Electrical DfT & Fault Coverage Analyzer TestWay's electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.

DFT- PRO Plus - A Comprehensive Package of DFT Tools DFT-PRO Plus  offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow

Mixed Radix DFT's (Matrix Range ) The Matrix range of cores is built around a set of different length DFT cores. When these different cores are combined, they allow an FFT to be configured to exactly match the number of points required for the application, with the most efficient FPGA utilisation. In one application, this type of core was also coupled with a rate converter core to provide a channeliser bank configured to exactly match the required output spacing and sample rate.

NEBULA Silicon Debugger - DFT validation and silicon debug platform NEBULA provides advanced features for performing early validation of DFT infrastructure and ATPG patterns in first silicon. The NEBULA solution directly imports test pattern formats and DFT information from leading EDA vendor tools, such as Synopsys' TetraMAX and Cadence's Encounter Test.

TurboDFT - Integration Tool Suite TurboDFT contains a suite of very useful and powerful DFT integration tools. TurboDFT allows users to automatically integrate and stitch DFT cores, whether they are created using DFT tools from SynTest or other vendors

WorkBench - (TWB) software Leverages your DFT to accelerate real-time, interactive scan validation, IC silicon debug and failure analysis

ScanBurst - Scan Insertion ScanBurst is an at-speed design for test (DFT) tool, designed to overcome the limitations of traditional at-speed DFT techniques. ScanBurst has been specifically engineered for full integration with Mentor Graphics' automatic test pattern generation (ATPG) products, TestKompress and FastScan, offering at-speed single-capture test application and support for hierarchical test generation and application. 

SpyGlass®-DFT - Design for Test at RTL The SpyGlass®-DFT solution has the unique ability to predict ATPG (automatic test pattern generation) test coverage and pinpoint testability issues as the RTL description is developed, even before a gate-level netlist is generated. The SpyGlass-DFT solution not only detects testability issues--it can also automatically correct them.

V550™ - Desktop Platform The Teseda V550™ is the latest generation of Teseda hardware platform designed for today's complex silicon validation and diagnostic challenges. The V550™ desktop platform, in conjunction with Teseda's TWB software, allows Design and DFT engineers to quickly validate initial silicon, thereby saving weeks in the silicon verification process.

DFT - Manager DFT Manager tool helps identify the nets on boards that require ICT access. It also helps to optimize the placement of physical access points on boards that have a mix of conventional and Boundary-Scan (JTAG) technology.

ART200 Development Station ELES is committed towards the full integration between the reliability and test environments, leveraging from DFT techniques. Today’s Development Station is the first step towards the objective of lowering the overall Cost-of-Quality for semiconductor manufacturers.

DFT 2100 - Flex Tester The Benz Model DFT 2100 flexing fatigue tester is a 20 station instrument designed to test the resistance to crack growth after repeated flexing. The instrument is capable of testing up to ten million cycles.The minimum cycle travel is 1/2 inch, to a maximum of 4 inches.

PSM2200 - Phase Sensitive Multimeter With synthesized signal generator, two isolated measurement channels, DFT and true rms analysis over a 100uHz to 2.4MHz frequency range, QuanteQ provides the ideal alternative to many separate test instruments. In either 19" rack or space-saving tower versions and with its wide range of accessories, PSM2200 QuanteQ provides the solution to many demanding measurement applications.

mTAT Series - Test System Enable Low Cost with best hardware configuration for device needs such as DFT (BIST integrated device). Enable Low Footprint with All-in-one test head structure adopting high level Integrated packaging of test circuit. Line up engineering testers for development & failure analysis and it contributes to reduce time of device programming and failure analysis on development.

ASIC / COT / FPGA Design EL & Associates, Inc. specializes in integrated solutions for design (RTL to GDSII), Design-For-Test (DFT) and Design-For-Manufacturing (DFM) services for ASIC, ASSP, COT, and FPGA. We engage with customers from RTL phase to silicon prototype. The ELA methodology is optimized to manage risk in design, manufacture and product deployment. ELA has successfully completed over 750 designs to date.

NetXY - Diagnostic Manager Teseda’s Diagnostic Manager NetXY enables failure analysis engineers to leverage the DFT features in your design to analyze captured tester fails and rapidly pinpoint the physical location of failures in silicon without requiring time-consuming device probing - reducing the time to localize faults by as much as 90%.

SD1000 - Phase Meter The SD1000 phase meter offers superb accuracy with a wide range of signal conditions.   Conventional phase meters are easily upset when small levels of noise and distortion are present - the result is often unstable and incorrect phase readings. The SD1000 overcomes this by using Discrete Fourier Analysis (DFT), this process rejects any noise and distortion without the need for tracking filters.