Showing results: 1 - 12 of 12 items found.
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Avery Design Systems
Complete solution for core through SoC level Host and Device Models Robust and flexible BFMs for all component types Comprehensive protocol checking Complete compliance testsuites Protocol analyzer trace logs reports Functional coverage of data/commands and sequences Intelligent producer-consumer scoreboard Native SystemVerilog/UVM support#1 in IP industry partnerships Superior domain expertise and customer support Compliance verification services
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Veloce -
Mentor Graphics Corp.
The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP). Mentor’s software and application solutions and continual enhancements enable a comprehensive verification environment for IP, chip, and system level verification.
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Cadence Design Systems
Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies.
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IC Manage, Inc.
IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Blue Pearl Software Inc
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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SD 3.0 / eMMC 4.51 IP Family -
Arasan Chip Systems, Inc.
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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SimAccel FPGA- -
Avery Design Systems
SimAccel combines advanced technology and methods for a comprehensive verification strategyRTL verification using VIPQEMU Virtual Host and embedded supporting x86, Arm, and RISC-VFPGA PrototypingUnified HW-SW DebugFull suite of Accelerated VIPPCIe, CXL, NVMe, DDR/LPDDR/HBM, AMBA, CPI/SFI, PIPE, LPIFThis allows the creation of domain-specific accelerator solutionsNVMePCIe/CXL chips (switch, retimer) and IP core-level
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JL-XC -
Lisun Electronics Inc.
JL-XC series waterproof test chamber is mainly used for small electronic and electrical products. Such as lamps, electrical cabinets, electrical components and so one. The products are tested for physical and other related properties under simulated climatic conditions. After the test, it is judged whether the performance of the product meets the requirements by verification, so as to be used in the design, improvement, verification and factory inspection of the product. Comply with IEC60529:2001 《Degrees of protection provided by enclosures (IP Code)》, GB4208-2008 《Shell Protection Grade (IP Code)》 14.2.8 Terms and GB7000.1 《Lamps Part 1: General Requirements and Tests》 9.2.9 Terms.
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Soundwire -
Arasan Chip Systems, Inc.
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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ALBEDO Telecom
Our product range comprises from small handheld, battery fed testers to full featured service performance assurance tools and distributed monitoring systems. We have several product lines including:QoS / SLA verification system Ethernet, IP, Critical Data, VoIP, IPTV .Hand-held testers: Gigabit Ethernet, Synchronous Ethernet, E1, PDH, SDH, Ethernet, IP, Jitter, Wander, Datacom, Frame Relay, etc.
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DSI -
Arasan Chip Systems, Inc.
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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QuickTest 500 -
Vonaq Ltd
*Rapid Testing. The QuickTest 500 ADSL2+ Tester's automatic Service Verification Test Suite starts as soon as you switch on (results are typically obtained in less than 3 minutes)*Simple to use. Virtually no product training required with QuickTest 500 ADSL Tester*Configurable Pass / Fail Indicators on the LCD display and clearly presented in multi-colour LEDs on the front panel*No need to get a laptop out*Save and name up to 16 test results at any one time*Line Voltage LED indicates poor, missing or excessive Line Voltage*ADSL/2/2+ Test LEDs to indicate if ADSL Showtime achieved*In Service LED indicates problems with PPP or IP layer*LEDs to indicate problems with the Trained Line Rate, poor Noise Margin or excessive Line Attenuation
