Verification IP
test and verify SoC's protocols and interface buses.
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Product
Specialized Extender Card Testing IP Modules
IP-Debug-Bus
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IP-Debug-Bus is a specialized extender card which is optimized for testing IP Modules. The bus signals are all accessible via test points. The testpoints include multiple ground locations and .025 sq. posts for ease of connection to your logic analyzer or scope. The testpoints are labeled for easy identification
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Product
96 Channel I/O and 64 Channel I/P VME Module
DP-VME-3132
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The DP-VME-3132 provides 96 channel RS422 differential digital I/Os and 64 channel RS422 differential isolated inputs on the front end and rear side. On the rear side, it is interfaced with the VME 64x backplane.
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Product
PAT and Installation Verification Unit
PowerCheck 1557
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The PowerCheck 1557 is a comprehensive PAT and installation verification checkbox. It carries out ongoing performance checks to ensure accurate measurement between calibration intervals. Fully tests Earth Continuity, Insulation Resistance, RCD Trip Time, RCD Trip Current, Loop, PE Conductor Current, Touch Current and Flash tests.
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Verification And Print Quality Inspection Solutions
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Integrate quality barcode verifiers within your production line using our robust barcode verification technology.
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NAND Controller IP
ONFI
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Arasan is the leading supplier of mobile storage IP and its products are used by most first tier memory suppliers. Arasan's deep experience with NAND flash memory interfaces and mobile storage standards began in 2001 when it joined the SD Association and shipped industry first SD card IP in 2003. Arasan is a current member of ONFI and JEDEC.
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Product
Phase Verification Bridges
5002
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Clarke-Hess Communications Research
The Model 5002 Phase Verification Bridge set comprises passive devices that are used in conjunction with Model 5500-2 Phase Standard and an output null indicator such as a true rms voltmeter, an oscilloscope or a wave analyzer to verify that the Phase Standard is continuing to operate within its specified phase accuracy limits.
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IP Reuse
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IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Product
Handheld Network Coverage Verification Tool
Nemo IoT Meter
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An easy-to-use handheld NB-IoT and LTE-M network coverage verification tool. Nemo IoT Meter is an easy-to-use handheld measurement tool for verifying IoT service quality at customer premises. Nemo IoT Meter can be used in industrial environments to verify coverage and end-to-end connection quality for IoT device installations. Ideal for technicians installing IoT probes and sensors, it runs on a regular Android-based smartphone and is connected through an NB-IoT or LTE-M dongle.
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Product
IP Video Stream Monitoring Probe
TSM Probe
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The Mividi TSM Probe is a compact system that runs Mividi TSM100 video streaming monitoring software and TSM Web remote management software on an Intel NUC PC. It receives data via IP interface and supports most common streaming protocols including TS over UDP, RTP, HTTP, HLS, RTMP, RTSP and MMS. The size of the device is only 4.5 x 1.9 x 4.4 inches, and it can be used for remote monitoring of IPTV and OTT video services in the proximity of customers.
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Product
Complete IP Module
Scan Ring Linker SRL
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The Scan Ring Linker SRLTM - is a complete IP module that can be easily embedded into a CPLD, FPGA or ASIC on a PCB to reduce the complexities and costs of designing 1149.1 (JTAG) test infrastructure for designs that use multiple scan rings. The SRL IP module links any number of scan rings (secondary scan paths) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single 1149.1 external interface.
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Rugged Cisco IP Router With Firewall & PoE+
NetSys-5311
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The rugged design of the NetSys-5311 brings Cisco’s ESR-6300 Embedded Services Router and its Cisco-certified mobile IP routing protocols to the network edge in a SWaP optimized chassis.
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Product
OEM Module For Conversion Between IP And ASI
DTM-3200
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The DTM-3200 converts IP to ASI, or ASI to IP. Integrate this compact module to extend the range of I/O standards supported by your product. Technical highlights include advanced IP-jitter filtering, ultra-low latency and zero-jitter IP transmission.
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Product
FPGA Image Processing (IP) Development Kit
ProcVision
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Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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Processor IP
System IP
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Perfect for high-efficiency IoT endpoint or a high performance server SoC.
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SoC Signoff & Structural Verification
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Defacto’s STAR augments existing RTL verification flows by providing fully automated structural checks. Users can also define and build their custom checks.
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Tools & IP
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The Developer’s Suite is based on more than 25 years of development and continuous improvement arising from valuable customer feedback. When used together with Intel’s design tools, the Developer’s Suite provides a market-unique solution that can achieve unmatched development productivity. The Gidel Developer’s Suite includes the following components:
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IP Cores & Software Tools
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Utilizes our Board Support Packages to get your hardware implementation underway as quickly as possible. The BSP gives you the control, flexibility and power to develop solutions for your most demanding digital signal processing applications.
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Product
ATSC 3.0 Broadcast Stream Verification
StreamScope XM Verifier
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The Windows®-based Verifier web app receives, tests, and records ATSC 3.0 broadcast streams from RF, Ethernet, and file inputs. With Verifier, you can monitor real-time graphs and charts of bitrates, signaling tables, RF parameters, packet errors, subframes, PLPs, and other KPIs.
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Product
PXI 32 Chan I/O Parallel I/P Prog Threshold
40-412-111
Digital I/O
A 32-channel Digital I/O module with high output voltage and currentcapability and a dual variable threshold input. Each of the 32 channel outputs can be used to drive the output high or low usinga high current capacity drive capable of sourcing 0.4A from the high side or 0.5Asink on the low side for each channel. The module is available in two versions witheither serial or parallel capture of the input levels.
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IP Core and FPGA Products
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Our FPGA offerings include development boards and IP cores for Altera FPGA devices. The IP cores include: I2C, PCIe, JPEG-LS, LVDS Camera Link and memory controllers.
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Product
Radio over IP Testing
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The transmission of data over the new generation of digital radio communications is proving increasingly popular with the emergency services, government, security, transport, construction, exploration, utilities and military sectors. However, RoIP/IP over Radio systems are frequently deployed in extremely challenging conditions such as natural disasters, storms, blackouts, difficult terrains (mountains, tall buildings) etc. Therefore, it is imperative that such systems are thoroughly tested prior to live deployment to ensure they will work effectively in potentially “life or death” situations.
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Product
Three Phase Closed I-P Link Energy Meter Test Bench Type KP-S3000-B
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Bofa Instrument & Equipment Co., Ltd
Three phase closed I-P link energy meter test bench, type KP-S3000-B, is designed for testing three-phase energy meters, especially for testing Closed I-P Links three-phase energy meters. It is an ideal testing equipment for energy meter factory or R&D institute. All the testing procedures can be automatically operated by PC or by Keyboard manually.
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Product
I/P Electro-Pneumatic Signal Converters
TEIP11 / TEIP11-PS
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Electro-pneumatic signal converters are the link between the control rooms and pneumatic actuators. I/P converters are available with and without booster stage.
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FPGA Verification
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The market is changing and rapidly expanding for FPGAs. Advancements in higher design frequency, embedded system FPGAs, and lower power consumption, combined with the reprogrammable advantages of FPGAs are increasing adoption into applications that have typically been enabled with ASSP/SoCs, including AI/ML, 5G, crypto, data center and high-performance computing applications.
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Envision Verification Analytics
Envision
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IC Manage Envision Verification Analytics provides:* Anytime, anywhere, data-driven insights allow engineers and management to rapidly identify and address problem areas to meet tight schedules spanning simulation, formal and emulation tools.* Utilizes big data technology to deliver near real-time verification analytics across the verification tool spectrum, for any mix of EDA vendors* With 10-100X the speed of traditional methods you can instantly understand your verification progress, at local and global levels.* Visual analytics and interactive reporting for regressions, bugs and coverage* Verification results linked to relevant design activity to help identify and resolve bottlenecks
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Hybrid Verification Platform
HES-DVM
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HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
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3U OpenVPX IP Router with 10GbE and 40GbE
ComEth4582a
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The 4582a implements a new generation of multi-layer Ethernet matrices for high speed embedded interconnect applications requiring low-power 10GbE and 40GbE connectivity. Designed in alignment with the SOSA™ standard.
