Advanced General Purpose FPGA

Advanced General Purpose FPGA

*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).
*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.
*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.

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