Showing results: 1 - 4 of 4 items found.
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782358-01 -
NI
40 GHz, Dual-Transfer PXI Transfer Switch Module—The PXI‑2798 can route RF or microwave signals in automated test applications. Designed to operate with less than 1 dB insertion loss at up to 40 GHz, the PXI‑2798 appears almost invisible to signals at much lower frequencies as well. You can use this module for basic signal routing or inserting and removing components in a signal path. The PXI‑2798 is also well-suited for passing high-order harmonics from RF upconverters or routing multiple sources to RF downconverters.
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778572-98 -
NI
26.5 GHz, 50 Ω, Dual-Transfer PXI Transfer Switch Module—The PXI‑2598 is a general-purpose switch module for routing RF or microwave signals in automated test applications. You can use this module for basic signal routing or inserting and removing components in a signal path. The PXI‑2598 is also well suited for passing high-order harmonics from PXI RF Signal Upconverter modules or routing multiple sources to PXI RF Signal Downconverter modules. You can use its onboard relay count tracking to predict relay lifetime and reduce unexpected system downtime.
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PAS 9797/DIO -
Precision Analog Systems Co.
The PAS 9797/DIO is a VME based, 160 Channel, TTL level, Digital Input / Output card. One hundred twenty eight channels are arranged as sixteen, byte wide bi-directional data ports. These are the primary data ports and support 32 bit transfers. The remaining thirty two channels are arranged as four byte wide bidirectional data ports. Each port consists of an eight bit output data register with output enable, and an eight bit input buffer.
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OneSpin Solutions GmbH
Functional correctness of FPGA synthesis from RTL code to final netlist. Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.
