Showing results: 421 - 422 of 422 items found.
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Patton Electronics Co.
What is a virtual session border controller or virtualized SBC? Traditionally, a session border controller (SBC) is a device positioned between carrier networks or between an enterprise LAN and a service-provider WAN. In the latter case, the border controller is called an enterprise session border controller or eSBC. Whether it is delivered as a dedicated hardware session border controller or a virtualized network function, (a.k.a. software SBC) the border controller manages call (session) setup and teardown. The SBC also provides network demarcation (demarc), or separation (border) between network domains, as well as other types of management (control) over the data streams that pass between networks. With the growing popularity of software defined networking (SDN) and the burgeoning market development and adoption of network function virtualization (NFV), eSBC functionality is more and more often de-coupled from a dedicated hardware device and delivered as a virtual instance running as a virtual machine (VM) on top of a hypervisor. It is generally not well understood in the market why an eSBC is such a critical network element for a secure and reliable SIP-based enterprise phone system. The following publication will help close that knowledge gap.
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ProcVision -
Gidel
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
