End Point IP Core

PCIe - Arasan Chip Systems, Inc. (Arasan)

The highly configurable PCIe End point IP core supports x1, x2, and x4 lane with a selection of 32/64-bit data path. Depending on design requirements, a maximum of 8 VCs and 8 TCs are supported. The IP core consists of many useful features that can be included to enhance system performance and to address special design needs in different applications. The data link layer allows the configuration of infinite credits to boost the flow control efficiency. By-pass mode, cut-through mode, and store-and-forward mode are other optional items. The transport layer features include configurable ECRC generation and checking, support for up to 64 configurable outstanding non-posted requests, and configurable payload size from 128 to 4 Kbytes