PLD For Bridging, Infinitely Reconfigurable I/O Expansion.

*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM
*SRAM based logic can be reconfigured in milliseconds using JTAG port
*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting
*Available in TQFP, csBGA, caBGA and ftBGA packages

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Topics

PLD
RAM
Analog
Clocks
Embedded
iOS
JTAG
Logic
LVDS
PCI
Phase
Polarization Extinction Ratio
SRAM