Showing results: 31 - 45 of 64 items found.
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Analog Devices Inc.
IF and RF Receivers are designed for communications infrastructure applications. Wide input bandwidth and high sample rates allow digitizing close to the antenna. Various receiver architectures, such as zero-IF, IF sampling to direct RF receivers, are supported and available on chip post digital signal processing can be used to offset demands in the FPGA or digital ASIC and ease analog filtering.
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Blue Pearl Software Inc
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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CX-400 Ver.2 -
Panasonic Industrial Devices Sales Company of America
For the CX-400 Series, the user has a large selection of ultra compact Photoelectric Sensors at his disposal. The Series includes three thru-beam, five retro-reflective, four diffuse reflective and four trigonometric types with foreground/background suppression. With its new ASIC (application specific integrated circuit), the Sensors require up to 60% less energy than before.
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SD 3.0 / eMMC 4.51 IP Family -
Arasan Chip Systems, Inc.
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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SCRAMNet+ SC150 -
Curtiss-Wright Defense Solutions
To enhance performance, The SCRAMNet+ SC150e products use an architecture where shared memory read operations bypass the SCRAMNet ASIC. DMA operations will have the greatest increase in performance in addition to better PIO and DMA operations. The overall performance becomes more effective as read latency is reduced, the number of PCI retries is decreased, and the PCI bus utilization is improved.
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DS-5 -
ARM Ltd.
ARM DS-5 is the tool-chain of choice for software developers who want to fully realize the benefits of the ARM Architecture. Comprising features such as the best-in-class ARM Compiler, powerful OS-aware debugger, system-wide performance analyzer, and real-time system simulator, DS-5 is an integrated development environment that assists engineers in delivering optimized and robust software for ARM processor-based ASICs and ASSPs.
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GRL-PCIE4-BASE-RXA -
Granite River Labs Inc.
GRL’s PCI Express®4.0 Base Specification Receiver Calibration and Test Automation Software for the Anritsu MP1800A BERT (GRL-PCIE4-BASE-RXA) provides an automated, simple, and efficient way to test your PCIe 4.0 Receiver to the Base (ASIC) Specification. GRL-PCIE4-BASE-RXA automates the MP1800A and Keysight real-time oscilloscope to calibrate the stressed eye opening and test Rx conformance.
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Analog Devices Inc.
Analog Devices silicon oscillators are frequency programmable via pin-strapping, or through the resistor connection or serial interface (SPI or I2C). These solid-state clocks are well-suited for general-purpose usage, such as PGAs, ASICS, microprocessors, or UARTS, and they operate from 1 kHz to 170 MHz. Silicon oscillators are also ideal switching regulator clocks as they provide synchronization and EMI reduction (via spread spectrum).
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ESCP-MIS1 Sensor -
ES Systems
ES Systems has developed a series of medium isolated pressure sensors suitable for applications with harsh environmental conditions where resistance to corrosive fluids or gases is required. Each sensor integrates a MEMS capacitive pressure sensor die, and a CMOS ASIC for the signal conditioning. The MEMS pressure sensor dies are underpinned by ES’s innovative microfabrication process for silicon capacitive sensors.
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Curtiss-Wright Defense Solutions
The 3U VPX (VITA 46 and 48.2) Flash Storage Module (FSM) provides high-performance, high-capacity, solid-state SATA storage with AES-256 bit encryption using an Application Specific Integrated Circuit (ASIC) that is FIPS-140-2 validated (Certification #1472). The 1" pitch conduction-cooled solid state storage device utilizes high reliability SLC NAND flash designed for the most demanding application.
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Dexter Research Center, Inc.
Dexter's Digital Detectors and Temperature Sensor Modules (TSM's) are based on Dexter's superior silicon thermopile technology and incorporate an ASIC that provides a cost effective front end for reading out the detector output. The digital solutions include pre-amplification, A/D, multi-plexing and SMBus communications. Additionaly, the SMBus can accommodate communications with up to 100 digital products. Our digital solutions are housed in industry standard TO-5/TO-39 packages.
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Renesas Electronics Corp.
Renesas' radiation hardened (rad hard) power products achieve the stringent voltage accuracy required of FPGAs, ASICs, microprocessors, and microcontrollers used in space and harsh environment applications. Our solutions enable regulation accuracy over input voltage, load current variation, switching noise, and large load transients and have proven highly reliable within mixed radiation exposure rates and other harsh environment variants.
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HES-DVM -
Aldec, Inc.
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
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Scan Ring Linker SRL -
Intellitech Corp.
The Scan Ring Linker SRLTM - is a complete IP module that can be easily embedded into a CPLD, FPGA or ASIC on a PCB to reduce the complexities and costs of designing 1149.1 (JTAG) test infrastructure for designs that use multiple scan rings. The SRL IP module links any number of scan rings (secondary scan paths) into a single high-speed test bus, which permits devices on secondary scan chains to be independently tested and configured through a single 1149.1 external interface.
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MaxLinear
PowerArchitect™ design and configuration software speeds development and significantly reduces overall time-to-market compared to legacy analog power solutions. An I²C interface and multiple GPIO pins ensure easy system integration. Configurable warning and fault levels, fault behavior and power up and down sequencing ensure any load can be properly powered and protected. The power system design can be completed with confidence long before the final revision of the SoC or ASIC is available.
