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J-BERT High-Performance BERT Configuration for Bench-Top 5-Slot Chassis

J-BERT High-Performance BERT Configuration for Bench-Top 5-Slot Chassis

Data rates up to 8.5/ 16 Gb/s for pattern generator and error detector1- 4 16 Gb/s BERT channels in a 5-slot AXIe chassisIntegrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, sinusoidal interference(common-mode and differential-mode), SSC (triangular and arbitrary, residual)8- tap de-emphasis (positive and negative) up to 20 dBInteractive link training for PCI ExpressBuilt-in clock data recovery and equalizationModules and options are upgradeableExtension to 32 Gb/s possible with M8061A multiplexer

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