Automatic Register Verification

ARV - Agnisys, Inc.

Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface. ARV helps to auto generate UVM test-bench bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences helps user to complete the verification right at first time.