Showing results: 1 - 4 of 4 items found.
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yieldWerx Semiconductor
Commonality Analysis (CA) refers to a set of statistical techniques to identify any systematic causes of yield loss. These techniques typically use association rules and/or ANOVA (Analysis of Variance) to identify manufacturing variables that are common to failed devices. Engineers use these techniques to narrow down the possible cause. This information helps in the decision
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yieldWerx Semiconductor
This module manages test program releases to both internal test facilities and OSAT’s. Supports creating the workflows that enable systematic and documented processes that minimize human error.
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yieldWerx Semiconductor
Gauge R&R provides an analysis technique for engineers to determine the amount of variability caused by a measurement system. For semiconductor devices to ensure that specifications can be guaranteed the repeatability and reproducibility of measurements need to be small relative to the measured specification tolerances. Primarily product and test engineers use this to assess test equipment. Yet with advanced design-for-test (DFT) based test methods which rely upon on-die circuitry to take a parametric measurement, design engineers should perform a Gauge R & R analysis to understand their on-die measurement variability.
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yieldWerx Semiconductor
For decades engineers have used STDF as the standard format for ATE test output- data logs, and yieldWerx automatically parses this format. However, with the increase in engineer’s usage of the general data record type (GDF) this usage often results in every product test program’s data log having a unique format from which you need to extract your data. Our support team can assist your company in this data extraction from STDF generated data logs using GDF record types.