Showing results: 1 - 5 of 5 items found.
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OneSpin Solutions GmbH
Unified, coverage-driven assertion-based verification, including a full automated apps library.
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OneSpin Solutions GmbH
Functional correctness of FPGA synthesis from RTL code to final netlist. Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.
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360 EC-RTL -
OneSpin Solutions GmbH
During a typical development process, there are many occasions where a change needs to be made to a block, which must then be retested to ensure functional equivalence. For example, once a block has been proven to operate correctly, a designer may wish to optimize some section, maybe to improve the coding style, reduce the gate count or streamline operation. Today, an engineer must execute an entire simulation regression run to verify each change. This often requires a lot of time and may also need additional stimulus, with no guarantee that an exhaustive functional check will be performed.
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OneSpin Solutions GmbH
ASIC synthesis verification from RTL code to final netlist.Systematic design errors, introduced by automated design refinement tools, such as ASIC synthesis, can be hard to detect, and damaging if they make it into the final device. Formal Equivalency Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized code.
