Showing results: 1 - 5 of 5 items found.
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SimCluster GLS -
Avery Design Systems
*Run post-layout, SDF-based gate-level simulation using multi-core and multiple server clusters.*Speed up simulation by 3-5X.*No design charges, no testbench charges, no SDF charges.
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SimXACT -
Avery Design Systems
Gate-Level X-Verification*Addressing X-pessimism in GLS is a must.*Detect simulation glitches.*Effectively root cause the source of real X's*Eliminate race conditions in 0-delay GLS.*Uncover testbench forcing and connectivity issues in GLS.*Complements other simulator-based X prop tools.
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Avery Design Systems
Complete solution for core through SoC level Host and Device Models Robust and flexible BFMs for all component types Comprehensive protocol checking Complete compliance testsuites Protocol analyzer trace logs reports Functional coverage of data/commands and sequences Intelligent producer-consumer scoreboard Native SystemVerilog/UVM support#1 in IP industry partnerships Superior domain expertise and customer support Compliance verification services
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SimAccel FPGA- -
Avery Design Systems
SimAccel combines advanced technology and methods for a comprehensive verification strategyRTL verification using VIPQEMU Virtual Host and embedded supporting x86, Arm, and RISC-VFPGA PrototypingUnified HW-SW DebugFull suite of Accelerated VIPPCIe, CXL, NVMe, DDR/LPDDR/HBM, AMBA, CPI/SFI, PIPE, LPIFThis allows the creation of domain-specific accelerator solutionsNVMePCIe/CXL chips (switch, retimer) and IP core-level
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Avery Design Systems
Level up and perform full System HW-SW verification at pre-silicon levelIterate HW and SW changes 10X faster at RTL compared to FPGA or system prototypesBegin HW-SW integration much sooner in development processVirtual machine to VIP co-sim/co-emulate environment extends existing SV/UVM testbench + VIPsX86 HostSupports PCIe/CXL root complex VIPRun Linux kernel drivers, compliance and benchmarking programs, and application softwareArm, RISC-V embedded systemsSupports AMBA (AXI/AHB/APB) VIPRun bare metal code or RTOS embedded systemsRun OS and SW unmodified from actual system configurationDebug trace shows QEMU to remote PCIe/CXL/AXI ports transactionsAvery's implementation of QEMU co-simulation is optimized for fastest performance including KVM mode and iWARP technologySimulations are scalable to 10s to 100s of instances for regression over OS versions and HW configurations