BIST

More Info
AKA:

Built In Self Test

Products (12)     Download
  • Pages:
  • 1
Definition:
"Built In Self Test" on-chip pseudo-random pattern generator.
Links:
Built-In Self Test of MEMS AccelerometersA built-in self-test technique that is applicable to symmetric microsystems such as the accelerometer is described. NILMONI DEB, R. D. BLANTON, August, 2004
Memory Chip BIST Architecture Paper describes a random access memory (RAM, sometimes also called an array) test scheme.
Wikipedia: BIST


Welcome