SAJE JTV - JTAG Verification

Ensures correct JTAG functionality on first-pass silicon. Verifies that BSDL customer file matches Verilog design. Generates high quality production test vectors. Helps find fab-related pad or JTAG logic yield problems.

SiliconAid Solutions, Inc.

1101 Capital of Texas Hwy South
Building H, Suite 215A
Austin, TX 78746
USA



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