SAJE JTS - JTAG Synthesis
Reads Verilog RTL or gate-level design (pre-JTAG) & generates a BSDL file. Synthesizes JTAG from BSDL and inserts results into design. Modifies pad instantiations to implement boundary scan registers. Adds instantiations to implement other JTAG functions. Includes library of synthesizable Verilog JTAG logic for JTAG functions. Complements SAJE JTV’s BSDL file-driven technology.
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SiliconAid Solutions, Inc.
1101 Capital of Texas Hwy South
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